The disclosed embodiments of the present invention relate to a digitally-controlled oscillator, and more particularly, to a method and an apparatus for measuring/compensating mismatches in a digitally-controlled oscillator.
A phase-locked loop (PLL) is an electronic control system that generates a signal that has a fixed relation to the phase of a reference signal. A PLL responds to both the frequency and the phase of the input signals, and automatically raises or lowers the frequency of a controlled oscillator until it is matched to the reference signal in both frequency and phase. As known by those skilled in the art, the performance of analog phase-locked loop (PLL) is getting worse with process scaling due to the less available voltage headroom, making all-digital phase-locked loop (ADPLL) prevails. Additionally, ADPLL may significantly help in area reduction and process migration. For example, a digital-controlled oscillator (DCO) may be used for replacing the conventionally used voltage-controlled oscillator (VCO) which is an analog element. A phase detector may also be replaced with a time-to-digital converter (TDC). Therefore, the usage of the ADPLL is becoming a trend in radio communications. For example, the ADPLL may be used in a direct frequency modulation (DFM) based transmitter such as a digital polar transmitter. Therefore, the capacitor mismatch in a tracking capacitor array of the DCO plays a crucial role in the transmitter (TX) modulation performance such as output radio frequency spectrum (ORFS). Besides, the systematic mismatch between integer and fractional tracking capacitors can also degrade ORFS.
There is thus a need for a built-in DCO self-calibration mechanism that is capable of measuring and compensating mismatches (e.g., capacitor mismatch and systematic mismatch) in the DCO without lengthy processing time.